Field
Disclosed embodiments generally relate to techniques for dealing with reliability issues in clocked systems. More specifically, disclosed embodiments relate to techniques where transmitter or receiver settings are changed during a transient period associated with a deterministic event, such as a change in a power state or clock start event for a personal computer or a mobile computing system.
Related Art
Extending battery life is a primary consideration in portable computing devices, such as laptop computers and smartphones. To conserve power, portable computing devices often halt clock signals to specific circuits until a later time. This clock-stopping technique is effective at reducing power consumption because the Complementary Metal Oxide Semiconductor (CMOS) circuitry within a portable computing device consumes substantially more power while the circuits are switching, and substantially less power while the circuits are idle.
Unfortunately, stopping and starting clock signals in a computer system can adversely affect system performance. To provide one example, a given integrated circuit (IC) within a computer system typically has a power delivery network (PDN), which comprises both on-chip and off-chip components. When a clock signal to the IC (or a clock signal inside the IC) is stopped to save power and then restarted, the IC immediately starts demanding power from the PDN. Because the PDN has a complex impedance, this sudden increase in demand for power causes a transient voltage response in the PDN. As a result, the voltage supplied to circuits with the IC typically starts to droop and can cause ringing. These voltage fluctuations can cause clock and data signals in the IC to have different delays, which can cause timing margins to decrease and thereby cause data errors.
These problems with voltage fluctuations can be avoided by simply waiting a period of time until the voltage fluctuations or other transient issues diminish. However, in computer systems where clock signals are stopped and started frequently, the extra waiting time can adversely affect computer system performance, for example, by delaying system response following a wake-up event.
Hence, what is needed is a method and an apparatus that supports stopping and starting clock signals within a computer system without the above-described problems.